(a) Fields of the Invention
The present invention relates to stacked semiconductor devices fabricated by stacking a plurality of semiconductor devices, and to lower modules of the stacked semiconductor devices.
(b) Description of Related Art
With a demand for size reduction and functionality enhancement of electronic equipment of various types including a cellular phone and a digital camera, electronic components, in particular stacked semiconductor devices with a plurality of semiconductor devices stacked therein are being developed.
For example, a structure of the device (see, for example, Japanese Unexamined Patent Publication No. 2004-363126) is shown which is made by stacking a first semiconductor package with a first semiconductor chip held therein and a second semiconductor package with a second semiconductor chip held therein.
For such a stacked semiconductor device, inspections of the semiconductor chips stacked therein cannot be made at the time of mounting of the individual chips, and the inspections should be made after completion of stacking. If the stacked semiconductor device inspected after the stacking is judged to be defective, the device in its entirety is discarded as defective or an additional process becomes necessary in which the mounted points of the device are disconnected one by one and the disconnect chips are mounted again. This results in poor yields.
In contrast to this, another structure of the stacked semiconductor device (see, for example, Japanese Unexamined Patent Publication No. 2004-281633) is shown which is made by stacking and mounting a plurality of chips and which includes a mounting terminal for use in mounting and an inspection terminal for use in inspecting the quality thereof.
In the case of the above structure, an inspection pad of a chip having been already mounted is first joined to an inspection terminal of another chip to be stacked, and then an inspection signal is received from the inspection pad of the mounted chip to carry out an inspection. If the result of the inspection is acceptable, a mounting terminal of the inspected chip to be mounted is connected to a mounting pad of the mounted chip, thereby mounting the chips.
However, since this stacked module is constructed so that the chips are directly held on a substrate, it is difficult to use this module for the case where packages are stacked which each have a chip mounted on a sub-substrate.
Furthermore, still another structure of the stacked semiconductor device (see, for example, Japanese Unexamined Patent Publication No. 2002-83897) is shown in which inspections of electrical properties can be conducted easily.
In this semiconductor device, first and second terminals are formed which are electrically connected to a semiconductor chip. With such a structure, the first terminal can be used for an electrical connection to another component, while the second terminal can be used for inspections of electrical properties.
Moreover, a structure of a grid array type semiconductor package (see, for example, Japanese Unexamined Patent Publication No. H9-223725) is shown in which a continuity test on the joint between a signal pin and a circuit pattern of a circuit substrate after surface mounting and an electrical test on the semiconductor package after completion of fabrication can be conducted easily.
However, as reduction in size and thickness of electronic equipment and technologies for thinning semiconductor chips go forward, the need for stacking semiconductor chips to enhance the functionality of the device is increasingly intensifying. In this case, a stacked semiconductor device is required on which tests for insuring the reliability of a semiconductor device to be stacked can be conducted before the stacking. For example, tests for the continuity of a connection terminal for making connection to a semiconductor device held in an upper layer and of a protruding electrode for making connection to external equipment are needed. However, for the conventional stacked semiconductor device exemplarily shown in Japanese Unexamined Patent Publication No. 2002-83897, certain tests on the device can be conducted by using the second terminal, but a test on the device even including the connection terminal for stacking cannot be conducted.
For the conventional stacked semiconductor device shown in Japanese Unexamined Patent Publication No. H9-223725, the signal pin and a contact pad can be used to conduct a continuity test. However, a probe coming into contact with the contact pad makes scratches, which easily induces poor connection in stacking. Moreover, test equipment used is expensive.